1. Cross-Reference to Related Applications
This application is related to application, Ser. No. 09/032,398, entitled MULTI-CHIP PACKAGING USING BUMP TECHNOLOGY, filed on the filing date of this application and assigned to the assignee of this application.
2. Field of the Invention
This invention relates generally to a method of interconnecting multiple semiconductor chips in a single package. More specifically, this invention relates to a method of interconnecting multiple semiconductor chips in a single package using flip chip technology. Even more specifically, this invention relates to a method of interconnecting multiple semiconductor chips in a single package using solder bump technology.
3. Discussion of the Related Art
The semiconductor industry is increasingly characterized by a growing trend towards integrating more integrated semiconductor circuits on a given semiconductor chip. In addition, the circuits are becoming more complex in order to provide the higher performance required by end users of the semiconductor chips. To achieve the higher performance demanded by end users it is necessary to not only provide more complexity in the circuits and functions, but also to ensure that the circuits are smaller and faster. This is being achieved by not only reducing the size of individual devices but by placing the circuits and circuit elements closer together. In turn, this means that more circuits have to be interconnected. Some of the circuits that are interconnected are on separate chips. The method of interconnection on a single chip as well as interconnections between separate chips must not detract from the performance and speed of the various functions on the semiconductor chips.
Interconnections provide paths or mediums for electrical signals that are delivered from source devices to destination or load devices. Because one of the major problems associated with interconnections is that the passage of electrical signals through interconnections takes time, the performance of the interconnected circuits is degraded. Another problem with interconnections is that interconnections have finite resistances that cause heat to be generated in the chips that must be dissipated. In order to decrease the time interval of the passage of electrical signals from one device to another and to decrease the amount of generated heat, the trend in the semiconductor industry is to integrate peripheral devices, such as cache memory devices, onto a single monolithic device. The integration of the peripheral devices onto a single chip improves signal processing, timing and performance of the integrated circuits as well as reduces generated heat. However, the integration places a greater strain on the fabrication of the integrated device.
With shrinking geometries and therefore greater device densities, an ever-smaller single defect can kill an entire single integrated device. As can be appreciated, the larger the die, the higher probability that a single defect can kill the device. Yield is a measure of good die obtained from a wager. Since net good die on a wafer is inversely proportional to the size of the die, one approach to increase yield would be to separate out the major components of a highly integrated device into its individual components on different chips. The resultant "silicon" yield of the individual components will exceed the silicon yield of the single monolithic device, by an appreciable measure.
One of the current methods to package semiconductor devices is flip chip technology in which a chip has either solder bumps or bond pads on the active face of the chip. Flip chip technology is defined as mounting the semiconductor chip to a substrate with any kind of interconnect materials and methods such as fluxless solder bumps, tape-automated bonding (TAB), wire interconnects, conductive polymers, anisotropic conductive adhesives, metallurgy bumps, compliant bumps, and pressure contacts as long as the active chip surface is facing the substrate (the package). In one method, the chip is placed face down onto a package so the solder bumps or bond pads on the chip are aligned and contact solder bumps or bond pads on the package. The device is reflowed (heated) so that the solder bumps and bond pads form metallurgical bonds.
Presently, there is a tradeoff between integrating more peripheral devices onto a single monolithic chip to achieve improved performance but with decreased yield or sacrificing performance for improved yield by using separate chips.
Therefore, what is needed is a method of interconnecting multiple semiconductor integrated circuits to obtain improved performance and at the same time obtaining improved yield.